Technical Field
The present disclosure relates to a line decoder for supplying control lines of a memory with positive or negative variable polarity voltages.
Description of the Related Art
Memories produced on CMOS (Complementary Metal-Oxide-Semiconductor) semiconductor substrate generally comprise a memory array in which memory cells are arranged in rows and in columns. The rows of memory cells are generally coupled to control lines and the columns of memory cells to bit lines.
Memory cells produced from floating-gate transistors are often erased by Fowler Nordheim effect (tunnel effect), by means of the channel erasing technique. Channel erasing requires a negative erase voltage to be applied to the control lines of the rows of memory cells that must be erased, while the substrate of the floating-gate transistors is taken to a positive voltage.
It may be desirable to simultaneously apply a positive voltage to memory cells not to be erased, to remove or limit the erasing stress of these memory cells. Such an erasing stress causes a slow spurious erasing which can lead to a full erasing of the memory cells not concerned by erasing operations. The erasing stress, if it cannot be avoided, must be managed, and requires providing a cyclical refreshing of the memory cells. This cyclical refreshing makes the structure of the memory significantly more complex and requires in particular executing a refreshing algorithm including a control of the threshold voltages of the floating-gate transistors.
The production of a line decoder capable of supplying a control line with a high value negative voltage while applying a high value positive voltage to other control lines of a memory array, for example −10V on the one hand and +10V on the other hand, comes up against various technological restrictions, in particular the fact that MOS transistors supplying such voltages cannot tolerate voltage differences greater than a breakdown voltage of these transistors, generally between 10V and 11V. It shall be recalled here that there are two types of breakdown in a MOS transistor: the breakdown of the gate oxide of the transistor and the breakdown of the junction PN or NP situated between the drain and the channel region or between the channel region and the source of the transistor. The junction breakdown generally occurs before the breakdown of the gate oxide and corresponds to a reverse-biased diode breakdown. A significant current leakage then occurs through the transistor, which causes the fall of the high erasing voltage supplied by charge pumps, generally of the order of 10V.
As a result, the voltage swing between negative and positive voltages simultaneously supplied by a conventional line decoder must not exceed the breakdown voltage of the transistors which supply these voltages. This technological limitation is found for example in the line decoder described by EP 1 441 360, which comprises terminating elements controlled by variable polarity signals supplied by group and sub-group decoders, and can simultaneously supply negative and positive voltages. As shown in FIGS. 5A to 5L of this document, which show the structure of the terminating elements, this decoder does not enable negative and positive voltages having a difference greater than the breakdown voltage of the transistors of the terminating elements to be simultaneously applied to a memory array. Thus, it is seen in Table 2, page 12 of this document, that the voltage swing never exceeds 9V.
Furthermore an architecture of sector-erasable memory array of the type schematically shown on FIG. 1 is known, in which a memory array is made up of several sectors, for example S(a), S(b), S(c), S(d), each implanted in a well electrically insulated from the wells receiving the other sectors. Each sector comprises rows of memory cells (not represented) coupled to control lines CL. The control lines of each sector are coupled to a dedicated line decoder LD(a), LD(b), LD(c), LD(d). Each line decoder is made in a well electrically insulated from the wells receiving the line decoders from other sectors, which forms the substrate of the memory cells. The sectors and their associated line decoders are thus electrically insulated from each other. This type of memory array architecture enables the well of a sector that must be erased to be biased with a positive voltage, while applying a zero voltage to the wells of the sectors not to be erased, such that their memory cells do not undergo any erasing stress. It is not therefore necessary to apply to the control lines of these sectors a negative voltage for neutralizing the erasing stress.
However, this type of memory array architecture divided into physical sectors produced in different wells occupies a semiconductor surface area that is much greater than that of an undivided memory array architecture, wherein all the memory cells are implanted in the same well and are controlled by a line decoder common to the entire memory array.
It could thus be desirable to provide a line decoder enabling lines of an undivided memory array to be simultaneously supplied with negative and positive voltages having a voltage difference greater than a breakdown voltage of transistors supplying these voltages.